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S25FL Family (Serial Peripheral Interface)
S25FL002D, S25FL001D 2 Megabit, 1 Megabit CMOS 3.0 Volt Flash Memory with 25 MHz SPI Bus Interface
PRELIMINARY INFORMATION
Distinctive Characteristics
ARCHITECTURAL ADVANTAGES
Single power supply operation -- Full voltage range: 2.7 to 3.6 V read and program operations Memory Architecture -- 2 Mb - Four sectors with 512 Kb each -- 1 Mb - Four sectors with 256 Kb each Program -- Page Program (up to 256 bytes) in 6 ms (typical) -- Program cycles are on a page by page basis Erase -- 0.25 s typical sector erase time (S25FL001D) -- 0.5 s typical sector erase time (S25FL002D) -- 1.0 s typical bulk erase time (S25FL001D) -- 2.0 s typical bulk erase time (S25FL002D) Endurance -- 100,000 cycles per sector typical Data Retention -- 20 years typical Device ID -- Electronic signature Process Technology -- Manufactured on 0.25 m process technology Package Option -- Industry Standard Pinouts -- 150 mil 8-pin SO package for 1Mb and 2Mb -- 208 mil 8-pin SO package for 2Mb only -- 8-contact WSON leadless package (6x5 mm)
PERFORMANCE CHARACTERISTICS
Speed -- 25 MHz clock rate (maximum) Power Saving Standby Mode -- Standby Mode 1 A (typical)
Memory Protection Features
Memory Protection -- W# pin works in conjunction with Status Register Bits to protect specified memory areas -- Status Register Block Protection bits (BP1, BP0) in status register configure parts of memory as readonly
SOFTWARE FEATURES
SPI Bus Compatible Serial Interface
Publication Number 30167
Revision A
Amendment +1
Issue Date June 9, 2004
Preliminary
Information
General Description
The S25FL002D and S25FL001D devices are 3.0 Volt (2.7 V to 3.6 V) single power supply Flash memory devices. S25FL002D consists of four sectors, each with 512 Kb memory. S25FL001D consists of four sectors, each with 256 Kb memory. Data appears on SI input pin when inputting data into the memory and on the SO output pin when outputting data from the memory. The devices are designed to be programmed in-system with the standard system 3.0 Volt VCC supply. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. The memory supports Sector Erase and Bulk Erase instructions. Each device requires only a 3.0 Volt power supply (2.7 V to 3.6 V ) for both read and write functions. Internally generated and regulated voltages are provided for the program operations. This device does not require VPP supply.
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Table of Contents
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .5 Input/Output Descriptions . . . . . . . . . . . . . . . . . . . 5 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . .6 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . .7 SPI Modes ...................................................................................................7
Figure 1. Bus Master and Memory Devices on the SPI Bus ....... 8 Figure 2. SPI Modes Supported............................................ 8 Figure 11. Page Program (PP) Instruction Sequence.............. 20
Sector Erase (SE) .................................................................................. 20
Figure 12. Sector Erase (SE) Instruction Sequence ............... 21
Bulk Erase (BE) ....................................................................................... 21
Figure 13. Bulk Erase (BE) Instruction Sequence .................. 22
Software Protect (SP) ......................................................................... 22
Figure 14. Software Protection (SP) Instruction Sequence...... 23
Release from Software Protect (RES) .............................................23
Figure 15. Release from Software Protect (RES) Instruction Sequence........................................................................ 24
Operating Features . . . . . . . . . . . . . . . . . . . . . . . . .9 Page Programming .................................................................................. 9 Sector Erase, or Bulk Erase ................................................................. 9 Polling During a Write, Program, or Erase Cycle ........................ 9 Status Register ......................................................................................... 9 Protection Modes ..................................................................................10
Table 1. Protected Area Sizes (S25FL002D). .........................10 Table 2. Protected Area Sizes (S25FL001D). .........................10
Release from Software Protection and Read Electronic Signature (RES), and Read ID (READ_ID) ....................................................... 24
Figure 16. Release from Software Protection and Read Electronic Signature (RES), and Read ID (READ_ID) Instruction Sequence........................................................................ 25
Power-up and Power-down . . . . . . . . . . . . . . . . . 26
Figure 17. Power-Up Timing............................................... 26 Table 7. Power-Up Timing ................................................. 27
Hold Condition Modes ........................................................................10
Figure 3. Hold Condition Activation...................................... 11
Memory Organization . . . . . . . . . . . . . . . . . . . . . . 12
Table 3. Sector Address Table - S25FL002D .........................12 Table 4. Sector Address Table - S25FL001D .........................12
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 5. Instruction Set. ....................................................13
Initial Delivery State . . . . . . . . . . . . . . . . . . . . . . . Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . .
27 27 27 27 28 29
Write Enable (WREN) ..........................................................................14
Figure 4. Write Enable (WREN) Instruction Sequence............. 14
Write Disable (WRDI) ........................................................................ 14
Figure 5. Write Disable (WRDI) Instruction Sequence ............ 14
Read Status Register (RDSR) ............................................................. 14
Figure 6. Read Status Register (RDSR) Instruction Sequence.. 15 Figure 7. Status Register Format......................................... 15
Figure 18. AC Measurements I/O Waveform......................... 29 Table 8. Test Specifications ............................................... 29 Table 9. AC Characteristics ................................................ 30 Figure 19. SPI Mode 0 (0,0) Input Timing ............................ 31 Figure 20. SPI Mode 0 (0,0) Output Timing.......................... 31 Figure 21. HOLD# Timing.................................................. 32 Figure 22. Write Protect Setup and Hold Timing during WRSR when SRWD=1 ....................................................... 32
Write Status Register (WRSR) .......................................................... 16
Figure 8. Write Status Register (WRSR) Instruction Sequence. 16 Table 6. Protection Modes ..................................................17
Read Data Bytes (READ) .................................................................... 17
Figure 9. Read Data Bytes (READ) Instruction Sequence ........ 18
Read Data Bytes at Higher Speed (FAST_READ) ....................... 18
Figure 10. Fast Read (FAST_READ) Instruction Sequence ....... 19
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . 33 S08 narrow--8-pin Plastic Small Outline 150mils Body Width Package ............................................................................33 S08 wide--8-pin Plastic Small Outline 208mils Body Width Package ............................................................................34 8-Contact WSON (6mm x 5mm) Leadless Package .................36
Page Program (PP) ................................................................................. 19
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Preliminary
Information
Block Diagram
SRAM
PS
Array - L Logic
X D E C
Array - R
RD
DATA PATH
IO
4
S25FL Family (Serial Peripheral Interface)
HOLD#
GND
CS#
SCK
VCC
SO
W#
SI
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Preliminary
Information
Connection Diagrams
8-pin Plastic Small Outline Package (SO) 8-contact WSON Package
CS# SO W# GND
1 2 3 4
8 7 6 5
VCC HOLD# SCK SI
CS# SO W# GND
1 2 3 4
8 7 6 5
VCC HOLD# SCK SI
Note: 1. 8-pin Plastic Small Outline Package (208 mils) offered for 2Mb density only.
Input/Output Descriptions
SCK SI SO CS# W# HOLD# VCC GND = = = = = = = = Serial Clock Input Serial Data Input Serial Data Output Chip Select Input Write Protect Input Hold Input Supply Voltage Input Ground Input
Logic Symbol
VCC
SI SCK CS# W# HOLD#
SO
GND
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Preliminary
Information
Ordering Information
The order number (Valid Combination) is formed by the following: S25FL 002 D 0F M A I 00 I
PACKING TYPE
1 3 00 01 I = Tube (standard; see Note 1) = 13" Tape and Reel (Note 2) = S0-8 Narrow (150 mils) package = S0-8 Wide (208 mils) package = Industrial (-40C to +85C)
MODEL NUMBER (Additional Ordering Options)
TEMPERATURE RANGE PACKAGE MATERIALS
A F M N = Standard = Lead (Pb)-free (Note 2) = 8 pin Plastic Small Outline Package = WSON (Note 2)
PACKAGE TYPE
SPEED
0F D = 25 MHz = 0.25 m process technology
DEVICE TECHNOLOGY DENSITY
002 001 = 2 Mb = 1 Mb
DEVICE FAMILY
SpansionTM Memory 3.0 Volt-only, Serial Peripheral Interface (SPI) Flash Memory
S25FL Valid Combinations Base Ordering Part Number S25FL002D 0F S25FL001D MAI, MFI, NFI 00 Speed Option Package & Temperature Model Number 00, 01 1, 3 (Note 1) Packing Type Package Marking (Note 3)
FL002D + (Temp) + (Last Digit of Model Number) (Note 4) FL001D + (Temp) + (Last Digit of Model Number) (Note 4)
Notes: 1. Type 1 is standard. Specify other options as required. 2. Contact your local sales office for availability. 3. Package marking omits leading "S25" and speed, package, and leading digit of model number from ordering part number. 4. If "Last Digit of Model Number" is `2', then this signifies a Lead (Pb)-free package. For example: FL002DI2 If "Last Digit of Model Number" is `0', this signified a standard package. For example: FL002DI0.
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device.
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Signal Description
Signal Data Output (SO): This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (SCK). Serial Data Input (SI): This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of Serial Clock (SCK). Serial Clock (SCK): This input signal provides the timing of the serial interface. Instructions, addresses, and data present at the Serial Data input (SI) are latched on the rising edge of Serial Clock (SCK). Data on Serial Data Output (SO) changes after the falling edge of Serial Clock (SCK). Chip Select (CS#): When this input signal is High, the device is deselected and Serial Data Output (SO) is at high impedance. Unless an internal Program, Erase or Write Status Register cycle is in progress, the device will be in Standby mode. Driving Chip Select (CS#) Low enables the device, placing it in the active power mode. After Power-up, a falling edge on Chip Select (CS#) is required prior to the start of any instruction. Hold (HOLD#): The Hold (HOLD#) signal is used to pause any serial communications with the device without deselecting the device. During the Hold instruction, the Serial Data Output (SO) is high impedance, and Serial Data Input (SI) and Serial Clock (SCK) are Don't Care. To start the Hold condition, the device must be selected, with Chip Select (CS#) driven Low. Write Protect (W#): The main purpose of this input signal is to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP1 and BP0 bits of the Status Register).
SPI Modes
These devices can be driven by a micro controller with its SPI peripheral running in either of the two following modes: CPOL = 0, CPHA = 0 CPOL = 1, CPHA = 1 For these two modes, input data is latched in on the rising edge of Serial Clock (SCK), and output data is available from the falling edge of Serial Clock (SCK). The difference between the two modes, as shown in Figure 2, is the clock polarity when the bus master is in Standby and not transferring data: SCK remains at 0 for (CPOL = 0, CPHA = 0) SCK remains at 1 for (CPOL = 1, CPHA = 1)
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SO
SPI Interface with (CPOL, CPHA) = (0, 0) or (1, 1) Bus Master
SI SCK SCK SO SI SCK SO SI SCK SO SI
SPI Memory Device CS3 CS2 CS1
CS# W# HOLD#
SPI Memory Device
SPI Memory Device
CS#
W# HOLD#
CS#
W# HOLD#
Figure 1. Bus Master and Memory Devices on the SPI Bus
Note: The Write Protect (W#) and Hold (HOLD#) signals should be driven, High or Low as appropriate.
CS# CPOL 0 1 CPHA 0 1 SCK SCK SI SO MSB MSB
Figure 2.
SPI Modes Supported
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Operating Features
All data into and out of the device is shifted in 8-bit chunks.
Page Programming
To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal Program cycle. To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the same page of memory.
Sector Erase, or Bulk Erase
The Page Program (PP) instruction allows bits to be programmed from 1 to 0. Before this can be applied, the bytes of the memory need to be first erased to all 1's (FFh) before any programming. This can be achieved in two ways: 1) a sector at a time using the Sector Erase (SE) instruction, or 2) throughout the entire memory, using the Bulk Erase (BE) instruction.
Polling During a Write, Program, or Erase Cycle
A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase (SE or BE) can be achieved by not waiting for the worst-case delay. The Write in Progress (WIP) bit is provided in the Status Register so that the application program can monitor its value, polling it to establish when the previous Write cycle, Program cycle, or Erase cycle is complete. Active Power and Standby Power Modes When Chip Select (CS#) is Low, the device is enabled, and in the Active Power mode. When Chip Select (CS#) is High, the device is disabled, but could remain in the Active Power mode until all internal cycles have completed (Program, Erase, Write Status Register). The device then goes into the Standby Power mode. The device consumption drops to ISB. This can be used as an extra software protection mechanism, when the device is not in active use, to protect the device from inadvertent Write, Program, or Erase instructions.
Status Register
The Status Register contains a number of status and control bits, as shown in Figure 7, that can be read or set (as appropriate) by specific instructions WIP bit: The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status Register, Program or Erase cycle. WEL bit: The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. BP1, BP0 bits: The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase instructions. SRWD bit: The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect (W#) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W#) signal allow the device to be put in the Hardware Protected mode. In this mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits.
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Preliminary
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Protection Modes
The SPI memory device boasts the following data protection mechanisms: All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events:
-- Power-up -- Write Disable (WRDI) instruction completion -- Write Status Register (WRSR) instruction completion -- Page Program (PP) instruction completion -- Sector Erase (SE) instruction completion
-- Bulk Erase (BE) instruction completion
The Block Protect (BP1, BP0) bits allow part of the memory to be configured as read-only. This is the Software Protected Mode (SPM). The Write Protect (W#) signal works in cooperation with the Status Register Write Disable (SRWD) bit to enable write-protection. This is the Hardware Protected Mode (HPM). Program, Erase and Write Status Register instructions are checked to verify that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution.
Table 1.
Protected Memory Area
Protected Area Sizes (S25FL002D).
Status Register Content BP1 Bit BP0 Bit 0 1 0 1 Protected Area none 30000-3FFFF 20000-3FFFF 00000-3FFFF
Memory Content Unprotected Area 00000-3FFFF 00000-2FFFF 00000-1FFFF none
0% 25% 50% 100%
0 0 1 1
Table 2.
Protected Memory Area
Protected Area Sizes (S25FL001D).
Status Register Content BP1 Bit BP0 Bit 0 1 0 1 Protected Area none 18000-1FFFF 10000-1FFFF 00000-1FFFF
Memory Content Unprotected Area 00000-1FFFF 00000-17FFF 00000-0FFFF none
0% 25% 50% 100%
0 0 1 1
Note:The device is ready to accept a Bulk Erase (BE) instruction, if and only if, both Block Protect (BP1 and BP0) are 0.
Hold Condition Modes
The Hold (HOLD#) signal is used to pause any serial communications with the device without resetting the clocking sequence. Hold (HOLD#) signal gates the clock input to the device. However, taking this signal Low does not terminate any Write Status Register, Program or Erase Cycle that is currently in progress.
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To enter the Hold condition, the device must be selected, with Chip Select (CS#) Low. The Hold condition starts on the falling edge of the Hold (HOLD#) signal, provided that this coincides with Serial Clock (SCK) being Low (as shown in Figure 3). The Hold condition ends on the rising edge of the Hold (HOLD#) signal, provided that this coincides with Serial Clock (SCK) being Low. If the falling edge does not coincide with Serial Clock (SCK) being Low, the Hold condition starts after Serial Clock (SCK) next goes Low. Similarly, if the rising edge does not coincide with Serial Clock (SCK) being Low, the Hold condition ends after Serial Clock (SCK) next goes Low (Figure 3). During the Hold condition, the Serial Data Output (SO) is high impedance, and Serial Data Input (SI) and Serial Clock (SCK) are Don't Care. Normally, the device remains selected, with Chip Select (CS#) driven Low, for the entire duration of the Hold condition. This ensures that the state of the internal logic remains unchanged from the moment of entering the Hold condition. Note: Driving Chip Select (CS#) high while HOLD# is still low is not a valid operation.
SCK HOLD#
Hold Condition (standard use)
Hold Condition (non-standard use)
Figure 3. Hold Condition Activation
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Memory Organization
The memory is organized as: S25FL002D: Four sectors of 512 Kbit each S25FL001D: Four sectors of 256 Kbit each Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector, or Bulk erasable (bits are erased from 0 to 1).
Table 3. Sector Address Table - S25FL002D
Sector SA3 SA2 SA1 SA0 Address Range 30000h 20000h 10000h 00000h 3FFFFh 2FFFFh 1FFFFh 0FFFFh
Table 4.
Sector SA3 SA2 SA1 SA0
Sector Address Table - S25FL001D
Address Range
18000h 10000h 08000h 00000h
1FFFFh 17FFFh 0FFFFh 07FFFh
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Instructions
All instructions, addresses, and data are shifted in and out of the device, starting with the most significant bit. Serial Data Input (SI) is sampled on the first rising edge of Serial Clock (SCK) after Chip Select (CS#) is driven Low. Then, the onebyte instruction code must be shifted in to the device, most significant bit first, on Serial Data Input (SI), each bit being latched on the rising edges of Serial Clock (SCK). The instruction set is listed in Table 5. Every instruction sequence starts with a one-byte instruction code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. Chip Select (CS#) must be driven High after the last bit of the instruction sequence has been shifted in. In the case of a Read Data Bytes (READ), Read Status Register (RDSR), Fast Read (FAST_READ) and Read ID (READ_ID), the shifted-in instruction sequence is followed by a data-out sequence. Chip Select (CS#) can be driven High after any bit of the data-out sequence is being shifted out to terminate the transaction. In the case of a Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status Register (WRSR), Write Enable (WREN), or Write Disable (WRDI) instruction, Chip Select (CS#) must be driven High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is, Chip Select (CS#) must driven High when the number of clock pulses after Chip Select (CS#) being driven Low is an exact multiple of eight. All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues unaffected
Table 5.
Instruction WREN WRDI WRSR RDSR READ FAST_READ READ_ID SE BE PP SP RES Description Write Enable Write Disable Write to Status Register Read from Status Register Read Data Bytes Read Data Bytes at Higher Speed Read ID Sector Erase Bulk (Chip) Erase Page Program Software Protect Release from Software Protect Release from Software Protect and Read Electronic Signature
Instruction Set.
Address Bytes 0 0 0 0 3 3 0 3 0 3 0 0 0 Dummy Byte 0 0 0 0 0 1 3 0 0 0 0 0 3 Data Bytes 0 0 1 1 to Infinity 1 to Infinity 1 to Infinity 1 to Infinity 0 0 1 to 256 0 0 1 to Infinity
One-Byte Instruction Code Status Register Operations 06H (0000 0110) 04H (0000 0100) 01H (0000 0001) 05H (0000 0101) Read Operations 03H (0000 0011) 0BH (0000 1011) ABH (1010 1011) Erase Operations D8H (1101 1000) C7H (1100 0111) Program Operations 02H (0000 0010) B9H (1011 1001) ABH (1010 1011) ABH (1010 1011)
Dummy Power Savings Mode Operations
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Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 4) sets the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Erase (SE or BE) and Write Status Register (WRSR) instruction. The Write Enable (WREN) instruction is entered by driving Chip Select (CS#) Low, sending the instruction code, and then driving Chip Select (CS#) High.
CS# 01 SCK Instruction SI High Impedance SO 234567
Figure 4. Write Enable (WREN) Instruction Sequence
Write Disable (WRDI)
The Write Disable (WRDI) instruction (Figure 5) resets the Write Enable Latch (WEL) bit. The Write Disable (WRDI) instruction is entered by driving Chip Select (CS#) Low, sending the instruction code, and then driving Chip Select (CS#) High. The Write Enable Latch (WEL) bit is reset under the following conditions: Power-up Write Disable (WRDI) instruction completion Write Status Register (WRSR) instruction completion Page Program (PP) instruction completion Sector Erase (SE) instruction completion Bulk Erase (BE) instruction completion
CS# 01234567 SCK Instruction SI High Impedance SO
Figure 5.
Write Disable (WRDI) Instruction Sequence
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Program, Erase, or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before
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sending a new instruction to the device. It is also possible to read the Status Register continuously, as shown in Figure 6.
CS# 01 SCK Instruction SI High Impedance SO Status Register Out Status Register Out 2 3 4 5 6 7 8 9 10 11 12 13 14 15
76543210765432107 MSB MSB
Figure 6. Read Status Register (RDSR) Instruction Sequence
b7 SRWD 0 0 BP1 BP0 WEL
b0 WIP
Status Register Write Disable Block Protect Bits Write Enable Latch Bit Write In Progress Bit
Figure 7. Status Register Format
The status and control bits of the Status Register are as follows: SRWD bit: The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect (W#) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W#) signal allow the device to be put in the Hardware Protected mode (when the Status Register Write Disable (SRWD) bit is set to 1, and Write Protect (W#) is driven Low). In this mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for execution. BP1, BP0 bits: The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase instructions. These bits are written with the Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 1 and Table 2) becomes protected against Page Program (PP), and Sector Erase (SE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. The Bulk Erase (BE) instruction is executed if, and only if, both Block Protect (BP1, BP0) bits are 0. WEL bit: The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1, the internal Write Enable Latch is set; when set to 0, the internal Write Enable Latch is reset and no Write Status Register, Program or Erase instruction is accepted.
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WIP bit: The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status Register, Program or Erase cycle. This bit is a read only bit and is read by executing a RDSR instruction. If this bit is 1, such a cycle is in progress, if it is 0, no such cycle is in progress.
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write Enable Latch (WEL). The Write Status Register (WRSR) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction code and the data byte on Serial Data Input (SI). The instruction sequence is shown in Figure 8. The Write Status Register (WRSR) instruction has no effect on bits b6, b5, b4, b1 and b0 of the Status Register. Bits b6, b5 and b4 are always read as 0. Chip Select (CS#) must be driven High after the eighth bit of the data byte has been latched in. If not, the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select (CS#) is driven High, the self-timed Write Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) is reset. The Write Status Register (WRSR) instruction allows the user to change the values of the Block Protect (BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table 1 and Table 2. The Write Status Register (WRSR) instruction also allows the user to set or reset the Status Register Write Disable (SRWD) bit in accordance with the Write Protect (W#) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W#) signal allow the device to be put in the Hardware Protected Mode (HPM). The Write Status Register (WRSR) instruction cannot be executed once the Hardware Protected Mode (HPM) is entered.
CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK Instruction Status Register In
SI High Impedance SO MSB
Figure 8. Write Status Register (WRSR) Instruction Sequence
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Table 6. Protection Modes
W# Signal 1 1 0 SRWD Bit 1 0 0 Software Protected (SPM) Mode Write Protection of the Status Register Protected Area (Note 1) Unprotected Area (Note 1) Ready to accept Page Program and Sector Erase Instructions
Status Register is Writeable (if the WREN instruction has set the WEL Protected against Page bit) Program and Erase (SE, BE) The values in the SRWD, BP1 and BP0 bits can be changed Status Register is Hardware write protected The values in the SRWD, BP1 and BP0 bits cannot be changed Protected against Page Program and Erase (SE, BE)
0
1
Hardware Protected (HPM)
Ready to accept Page Program and Sector Erase Instructions
5. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 1 and Table 2. The protection features of the device are summarized in Table 6. When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial delivery state), it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless of the whether Write Protect (W#) is driven High or Low. When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two cases need to be considered, depending on the state of Write Protect (W#): If Write Protect (W#) is driven High, it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. If Write Protect (W#) is driven Low, it is not possible to write to the Status Register even if the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. (Attempts to write to the Status Register are rejected, and are not accepted for execution). As a consequence, all the data bytes in the memory area that are software protected (SPM) by the Block Protect (BP1, BP0) bits of the Status Register, are also hardware protected against data modification. Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be entered: by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W#) Low or by driving Write Protect (W#) Low after setting the Status Register Write Disable (SRWD) bit. The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write Protect (W#) High. If Write Protect (W#) is permanently tied High, the Hardware Protected Mode (HPM) can never be activated, and only the Software Protected Mode (SPM), using the Block Protect (BP1, BP0) bits of the Status Register, can be used.
Read Data Bytes (READ)
The device is first selected by driving Chip Select (CS#) Low. The instruction code for the Read Data Bytes (READ) instruction is followed by a 3-byte address (address bits A23 to A18 are Don't Care), each bit being latched-in during the rising edge of Serial Clock (SCK). Then the memory contents, at that address, are
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shifted out on Serial Data Output (SO), each bit being shifted out, at a frequency fSCK, during the falling edge of Serial Clock (SCK). The instruction sequence is shown in Figure 9. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) instruction. When the highest address is reached, the address counter rolls over to 00000h, allowing the read sequence to be continued indefinitely. The Read Data Bytes (READ) instruction is terminated by driving Chip Select (CS#) High. Chip Select (CS#) can be driven High at any time during data output. Any Read Data Bytes (READ) instruction, while a Program, Erase, or Write cycle is in progress, is rejected without having any effect on the cycle that is in progress.
CS# 0 1 2 3 4 5 6 7 8 9 10 SCK
Instruction 24-Bit Address
28 23 30 31 32 33 34 35 36 37 38 39
SI
High Impedance
23 22 21
MSB
3210
Data Out 1 Data Out 2
SO
765432
MSB
107
Figure 9. Read Data Bytes (READ) Instruction Sequence
Read Data Bytes at Higher Speed (FAST_READ)
The Fast Read (FAST_READ) instruction implemented in this device is compatible with industry standard Fast Read (FAST_READ) operations. The device is first selected by driving Chip Select (CS#) Low. The instruction code for (FAST_READ) instruction is followed by a 3-byte address (A23-A0 for 2Mbit devices) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (SCK). Then the memory contents, at that address, are shifted out on Serial Data Output (SO), each bit being shifted out, at a maximum frequency FSCK, during the falling edge of Serial Clock (SCK). The instruction sequence is shown in Figure 10. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single (FAST_READ) instruction. When the highest address is reached, the address counter rolls over to 00000h, allowing the read sequence to be continued indefinitely. The (FAST_READ) instruction is terminated by driving Chip Select (CS#) High. Chip Select (CS#) can be driven High at any time during data output. Any
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(FAST_READ) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.
CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCK
Instruction 23 22 21 24-Bit Address 3 2 1 0 7 6 Dummy Byte 5 4 2 0 DATA OUT 1 DATA OUT 2 1 0 7 MSB
SI SO
High Impedance
3
1
7 MSB
6
5
4
3
2
Figure 10.
Fast Read (FAST_READ) Instruction Sequence
Page Program (PP)
The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Page Program (PP) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction code, three address bytes and at least one data byte on Serial Data Input (SI). Chip Select (CS#) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 11. If more than 256 bytes are sent to the device, the addressing will wrap to the beginning of the same page, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If fewer than 256 Data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. Chip Select (CS#) must be driven High after the eighth bit of the last data byte has been latched in, otherwise the Page Program (PP) instruction is not executed. As soon as Chip Select (CS#) is driven High, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Page Program (PP) instruction applied to a page that is protected by the Block Protect (BP1, BP0) bits (see Table 1 and Table 2) is not executed.
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CS#
0 1 2 3 4 5 6 7 8 9 10
SCK
28 29 30 31 32 33 34 35 36 37 38 39
Instruction
24-Bit Address
Data Byte 1
SI
23 22 21 MSB
3
2
1
0
7
6
5
4
3
2
1
0
MSB
2072
7 MSB
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCK
Data Byte 2
Data Byte 3
SI
7 MSB
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
6
MSB
Figure 11.
Page Program (PP) Instruction Sequence
Sector Erase (SE)
The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Sector Erase (SE) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction code, and three address bytes on Serial Data Input (SI). Any address inside the Sector (see Table 1 and Table 2) is a valid address for the Sector Erase (SE) instruction. Chip Select (CS#) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 12. Chip Select (CS#) must be driven High after the eighth bit of the last address byte has been latched in, otherwise the Sector Erase (SE) instruction is not executed. As soon as Chip Select (CS#) is driven High, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Sector Erase (SE) instruction applied to any memory area that is protected by the Block Protect (BP1, BP0) bits (see Table 1 and Table 2) is not executed.
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S25FL Family (Serial Peripheral Interface)
2073 2074 2075 2076 2077 2078 2079
Data Byte 256 5 4 3 2 1 0
CS#
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CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
SCK
Instruction 24 Bit Address
SI
23 22 21 MSB
Figure 12.
3
2
1
0
Sector Erase (SE) Instruction Sequence
Bulk Erase (BE)
The Bulk Erase (BE) instruction sets to 1 (FFh) all bits inside the entire memory. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Bulk Erase (BE) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction code, on Serial Data Input (SI). No address is required for the Bulk Erase (BE) instruction. Chip Select (CS#) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 13. Chip Select (CS#) must be driven High after the eighth bit of the last address byte has been latched in, otherwise the Bulk Erase (BE) instruction is not executed. As soon as Chip Select (CS#) is driven High, the self-timed Bulk Erase cycle (whose duration is tBE) is initiated. While the Bulk Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Bulk Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Bulk Erase (BE) instruction is executed only if both the Block Protect (BP1, BP0) bits (see Table 1 and Table 2) are set to 0. The Bulk Erase (BE) instruction is ignored if one or more sectors are protected.
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CS#
0
1
2
3
4
5
6
7
SCK
Instruction
SI
Figure 13. Bulk Erase (BE) Instruction Sequence
Software Protect (SP)
The Software Protect (SP) instruction implemented in this device is compatible with industry-standard Software Protect (SP) operation. For this device, this instruction has no real function since the Standby Current (ISB) on this device is the same as the Deep Power-down Current in our competitor's devices. It is recommended that the standard Standby mode be used for the lowest power current draw, as well as the Software Protect (SP) as an extra software protection mechanism when this device is not in active use. In this mode, the device ignores all Write, Program and Erase instructions. Chip Select (CS#) must be driven Low for the entire duration of the sequence. The Software Protect (SP) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction code on Serial Data Input (SI). Chip Select (CS#) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 14. Driving Chip Select (CS#) High after the eighth bit of the instruction code has been latched in deselects the device, and puts the device in the Standby mode (if there is no internal cycle currently in progress). As soon as Chip Select (CS#) is driven high, it requires a delay of tSP currently in progress before Software Protect mode is entered. Once the device has entered the Software Protect mode, all instructions are ignored except the Release from Software Protect (RES) or Read ID (READ_ID) instruction. The Release from Software Protect and Read Electronic Signature (RES) instruction also allows the Electronic Signature of the device to be output on Serial Data Output (SO). The Software Protect mode automatically stops at Power-down, and the device always Powers-up in the Standby mode.
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Any Software Protect (SP) instruction, while an Erase, Program or WRSR cycle is in progress, is rejected without having any effect on the cycle in progress.
CS#
tSP 0 1 2 3 4 5 6 7
SCK Instruction
SI
Standby Mode
Software Protect Mode
Figure 14. Software Protection (SP) Instruction Sequence
Release from Software Protect (RES)
The Release from Software Protect (RES) instruction provides the only way to exit the Software Protect mode. Once the device has entered the Software Protect mode, all instructions are ignored except the Release from Software Protect (RES) instruction. The Release from Software Protect (RES) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction code on Serial Data Input (SI). Chip Select (CS#) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 15. Driving Chip Select (CS#) High after the 8-bit instruction byte has been received by the device, but before the whole of the 8-bit Electronic Signature has been transmitted for the first time, still insures that the device is put into Standby mode. If the device was previously in the Software Protect mode, though, the transition to the Stand-by Power mode is delayed by tRES, and Chip Select (CS#) must remain High for at least tRES(max), as specified in Table 7. Once in the Standby Power mode, the device waits to be selected, so that it can receive, decode and execute instructions.
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CS#
0 SCK
1
2
3
4
5
6
7
Instruction
tRES
SI
Software Protect Mode
Figure 15.
Standby Mode
Release from Software Protect (RES) Instruction Sequence
Release from Software Protection and Read Electronic Signature (RES), and Read ID (READ_ID)
Once the device has entered SP mode, all instructions are ignored except the RES instruction. The RES instruction can also be used to read the 8-bit Electronic Signature of the device on the SO pin. The RES instruction always provides access to the Electronic Signature of the device (except while an Erase, Program or WRSR cycle is in progress), and can be applied even if SP mode has not been entered. Any RES instruction executed while an Erase, Program or WRSR cycle is in progress is not decoded, and has no effect on the cycle in progress. The Read ID (READ_ID) instruction can be used to read, on Serial Data Output (SO), the 8-bit Electronic Signature of the device. Except while an Erase, Program or Write Status Register cycle is in progress, the Read ID (READ_ID) instruction always provides access to the Electronic Signature of the device, and can be applied even if the Software Protect mode has not been entered. Any Read ID (READ_ID) instruction while an Erase, Program or Write Status Register cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. The device features an 8-bit Electronic Signature, whose value for the S25FL002D is 11h, S25FL002D is 10h. This can be read using Read ID (READ_ID) instruction. The device is first selected by driving Chip Select (CS#) Low. The instruction code is followed by 3 dummy bytes, each bit being latched-in on Serial Data Input (SI) during the rising edge of Serial Clock (SCK). Then, the 8-bit Electronic Signature, stored in the memory, is shifted out on Serial Data Output (SO), each bit being shifted out during the falling edge of Serial Clock (SCK). The instruction sequence is shown in Figure 16. The Read ID (READ_ID) instruction is terminated by driving Chip Select (CS#) High after the Electronic Signature has been read at least once. Sending addi-
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tional clock cycles on Serial Clock (SCK), while Chip Select (CS#) is driven Low, causes the Electronic Signature to be output repeatedly. When Chip Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the Software Protect mode, which occurs when the Read ID (READ_ID) instruction is initiated, the transition to the Stand-by Power mode is immediate. If the device was previously in the Software Protect mode, though, the transition to the Standby mode is delayed by tRES, and Chip Select (CS#) must remain High for at least tRES(max), as specified in Table 9. Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions.
CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38
SCK
Instruction 3 Dummy Bytes
23 22 21 MSB 32 1 0 Electronic ID out 7 MSB Software Protect Mode Standby Mode 6 5 4 3 2 1 0
tRES
SI SO
High Impedance
Figure 16. Release from Software Protection and Read Electronic Signature (RES), and Read ID (READ_ID) Instruction Sequence
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Power-up and Power-down
The device must not be selected at power-up or power-down (that is, CS# must follow the voltage applied on VCC) until VCC reaches the minimum correct value, as follows: VCC (min) at power-up, and then for a further delay of tPU (as described in Table 7) VSS at power-down A simple pull-up resistor on Chip Select (CS#) can usually be used to insure safe and proper power-up and power-down. To avoid data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is included. The logic inside the device is held reset while VCC is less than the POR threshold value (VPOR). All operations are disabled, and the device does not respond to any instructions. The device ignores all instructions until a time delay of tPU (as described in Table 7) has elapsed after the moment that VCC rises above the minimum VCC threshold. However, correct operation of the device is not guaranteed if by this time VCC is still below VCC (min). No Read, Write Status Register, Program or Erase instructions should be sent until tPU after VCC reaches the minimum VCC threshold. At power-up, the device is in Standby mode (not Software Protect mode) and the WEL bit is reset. Normal precautions must be taken for supply rail decoupling to stabilize the VCC feed. Each device in a system should have the VCC rail decoupled by a suitable capacitor close to the package pins (this capacitor is generally of the order of 0.1 F). At power-down, when VCC drops from the operating voltage to below the minimum VCC threshold, all operations are disabled and the device does not respond to any instructions. (The designer needs to be aware that if a power-down occurs while a Write, Program or Erase cycle is in progress, data corruption can result.)
*Note:
Program, Erase, and Write Commands are not allowed and are not recommended during this period, as the state of the device operation is unknown during tPU.
VCC VCC (max)
*Note
VCC (min)
Reset State of the Device tPU Device fully accessible
VPOR
time
Figure 17. Power-Up Timing
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Table 7. Power-Up Timing
Symbol tPU VPOR Parameter VCC (min) to CS# Low POR Threshold Value Min 2 2.2 2.4 Max Unit ms V
Initial Delivery State
The device is delivered with all bits set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0).
Maximum Rating
Stressing the device above the rating listed in the Absolute Maximum Ratings section below may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability
Absolute Maximum Ratings
Ambient Storage Temperature . . . . . . . . . . . . . . . . . . . . . -65C to +150C Voltage with Respect to Ground: All Inputs and I/Os. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4.5 V
Operating Ranges
Ambient Operating Temperature (TA) Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C Positive Power Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 V to 3.6 V
Operating ranges define those limits between which functionality of the device is guaranteed.
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DC Characteristics
This section summarizes the DC and AC Characteristics of the device. Designers should check that the operating conditions in their circuit match the measurement conditions specified in the Test Specifications in Table 8, when relying on the quoted parameters.
CMOS Compatible
Parameter Description VCC ICC1 ICC2 ICC3 ICC4 ICC5 ISB ILI ILO VIL VIH VOL VOH Supply Voltage VCC Active Read Current SCK = 0.1 VCC/0.9VCC 25 MHz VCC = 3.0V Test Conditions (Note 1) Min 2.7 Typ. 3 9 10 Max 3.6 12 16 20 20 20 1 3 1 1 -0.3 0.7 VCC IOL = 1.6 mA, VCC = VCC min IOH = -0.1 mA VCC - 0.2 0.3 VCC VCC + 0.5 0.4 Unit V mA mA mA mA mA A A A V V V V
VCC Active Page Program Current CS# = VCC VCC Active WRSR Current VCC Active Sector Erase Current VCC Active Bulk Erase Current Standby Current Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage CS# = VCC CS# = VCC CS# = VCC CS# = VCC = 3.0 V VIN = GND to VCC VIN = GND to VCC
Note:
1. Typical values are at TA = 25C and 3.0 V.
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Test Conditions
Input Levels 0.8 VCC Input and Output Timing Reference levels 0.7 VCC 0.3 VCC
0.2 VCC
Figure 18. AC Measurements I/O Waveform Table 8.
Symbol CL Parameter Load Capacitance Input Rise and Fall Times Input Pulse Voltage Input and Output Timing Reference Voltages
Test Specifications
Min 30 5 0.2 VCC to 0.8 VCC 0.3 VCC to 0.7 VCC Max Unit pF ns V V
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AC Characteristics
Table 9.
Parameter SCK Clock Frequency Clock Rise Time (Slew Rate) Clock Fall Time (Slew Rate) SCK High Time SCK Low Time CS# High Time CS# Setup Time CS# HOLD Time HOLD# Setup Time HOLD# Hold Time HOLD Setup Time (relative to tHC SCK) HOLD Hold Time (relative to tCH SCK) tV Output Valid tHO Output Hold Time tHD:DAT Data in Hold Time tSU:DAT Data in Setup Time tLZ (Note 3) HOLD# to Output Low Z tHZ (Note 3) HOLD# to Output High Z tDIS (Note 3) Output Disable Time tWPS (Note 3) Write Protect Setup Time tWPH (Note 3) Write Protect Hold Time tRES Release SP Mode CS# High to Software Protect tSP Mode tW Write Status Register Time tPP (Note 1) Page Programming Time tSE Sector Erase Time 512 Kb Sector (S25FL002D) 256 Kb Sector (S25FL001D) 1 Mb device 2 Mb device Symbol FSCK (Note 4) tCRT tCFT tWH tWL tCS tCSS (Note 3) tCSH (Note 3) tHD (Note 3) tCD (Note 3)
AC Characteristics
Min 0.1 0.1 18 18 100 10 10 10 10 10 10 0 0 5 5 15 Typ Max 25 Unit MHz V/ns V/ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s s ms ms sec sec
15 20 15 20 100 1.0 3.0 1.6 6 (Note 1) 0.5 (Note 1) 15 (Note 2) 10 (Note 2) 0.8 (Note 2)
0.25 (Note 1) 0.4 (Note 2) 1.0 (Note 1) 2.0 (Note 1) 1.6 (Note 2)
tBE
Bulk Erase Time
sec 3.2 (Note 2)
Note:
1. Typical program and erase time assume the following conditions: 25C, VCC = 3.0V; 10,000 cycles; checkerboard data pattern. 2. Under worst-case conditions of 90C; VCC = 2.7V; 100,000 cycles. 3. Not 100% tested 4. Both for READ and FAST_READ
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AC Characteristics
tCS
CS#
tCSH
tCSS
tCSH
tCSS
SCK
tCRT tSU:DAT tHD:DAT tCFT
SI MSB IN LSB IN
High Impedance SO
Figure 19.
SPI Mode 0 (0,0) Input Timing
CS#
tWH
SCK
tV tV tHO tHO tWL tDIS
SO
LSB OUT
Figure 20. SPI Mode 0 (0,0) Output Timing
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AC Characteristics
CS#
tCH
tHD
tHC
SCK
tCD tHZ tLZ
SO
SI
HOLD#
Figure 21.
HOLD# Timing
W#
tWPS
tWPH
CS#
SCK
SI
SO
High Impedance
Figure 22. Write Protect Setup and Hold Timing during WRSR when SRWD=1
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Physical Dimensions
S08 narrow--8-pin Plastic Small Outline 150mils Body Width Package
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Physical Dimensions
S08 wide--8-pin Plastic Small Outline 208mils Body Width Package
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S08 wide--8-pin Plastic Small Outline 208mils Body Width Package (Continued) Design Note:
This note is for the S25FL002D device only. It is recommended that during PCB Layout, pads be placed on the board to accommodate both Spansion's SO-8 narrow and wide footprints. This will allow for a smooth upgrade path to our 4Mb and 8Mb SPI devices, without the need to relayout the board. In order to simplify layout, only one set of pads needs to be added to the board to accommodate the 208 mils SO-8 wide package. Because the pinouts of both the narrow and wide footprint parts are the same, no jumpers need to be placed on the board.
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Physical Dimensions
8-Contact WSON (6mm x 5mm) Leadless Package
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Revision Summary
Revision A (November 7, 2003)
Initial release.
Revision A+1 (June 9, 2004)
Minor corrections, updated 8-pin SOIC package diagram. Updated notes for Table 9. AC Characteristics. Removed 512Kb offering. Removed Page Erase (PE) Functionality. Added the wide 8-pin SO (208mils) package. Added design note for 2Mb. Added the 8-Contact WSON (6mm x 5mm) leadless package.
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Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by FASL LLC. FASL LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. FASL LLC assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright (c) 2004 FASL LLC. All rights reserved. Spansion, the Spansion logo, MirrorBit, combinations thereof, and ExpressFlash are trademarks of FASL LLC. Other company and product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
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